Joseph Zambreno

  • Associate Professor

Main Office

327 Durham
Ames, IA 50011-2252
Phone: 515-294-3312

Interest Areas

Reconfigurable computing, computer security, compilers, computer architecture

Core Research Area: Computing and networking systems

Strategic Research Area: Cyber infrastructure

Selected Publications

Baumgarten, Alex, Akhilesh Tyagi, and Joseph Zambreno. Preventing IC Piracy Using Reconfigurable Logic Barriers. IEEE Design and Test of Computers 27, no. 1 (February 2010): 66-75.

Pande, A. and J. Zambreno. A Reconfigurable Architecture for Secure Multimedia Delivery. In Proc. International Conference on VLSI Design , Bangalore, India, January 3-4, 2010: 258-263.

Pande, A. and J. Zambreno. "An Efficient Hardware Architecture for Multimedia Encryption and Authentication using the Discrete Wavelet Transform. In Proc. IEEE Computer Society Annual Symposium on VLSI , (May 2009): 85-90.

Sun, S. and J. Zambreno. "Mining Association Rules with Systolic Trees. In Proc. International Conference on Field-Programmable Logic and its Applications , (September 2008): 143-148.

Nguyen, D., A. Das, J. Zambreno, G. Memik, and A. Choudhary. "An FPGA-Based Network Intrusion Detection Architecture. IEEE Transactions on Information Forensics and Security 3, no. 1, (2008): 118-132.