Joseph Zambreno


Ross Martin Mehl and Marylyne Munas Mehl Computer Engineering Professor


2218 Coover
613 Morrill Rd.
Ames, IA 500112100



Ph.D., Northwestern University Evanston, IL Electrical and Computer Engineering (2006)

M.S., Northwestern University Evanston, IL Electrical and Computer Engineering (2002)

B.S., Northwestern University Evanston, IL Computer Engineering (2001)

Research Areas

Core Area(s): Computing and networking systems, secure and reliable computing

Department’s Strategic Area(s): Cyber infrastructure; energy infrastructure

Personal Website


Google Scholar Profile:

  • Joshua Bertram, Joseph Zambreno, and Peng Wei, “Efficient Unmanned Aerial Systems Navigation With Collision Avoidance in Dense Urban Environments”, IEEE Transactions on Intelligent Transportation Systems (T-ITS), Aug 2023
  • Uchenna Ezeobi, Habeeb Olufowobi, Clinton Young, Joseph Zambreno, and Gedare Bloom, “Reverse Engineering Controller Area Network Messages using Unsupervised Machine Learning”, IEEE Consumer Electronics Magazine, Jan 2022
  • Murad Qasaimeh, Kristof Denolf, Alireza Khodamoradi, Michaela Blott, Jack Lo, Lisa Halder, Kees Vissers, Joseph Zambreno, and Phillip Jones, “Benchmarking Vision Kernels and Neural Network Inference Accelerators on Embedded Platforms”, Journal of Systems Architecture, Feb 2021
  • Saunak Saha, Henry Duwe, and Joseph Zambreno, “CyNAPSE: A Low-power Reconfigurable Neural Inference Accelerator for Spiking Neural Networks”, Journal of Signal Processing Systems, Feb 2020
  • Alex Grieve, Michael Davies, Phillip Jones, and Joseph Zambreno, “ARMOR: A Recompilation and Instrumentation-free Monitoring Architecture for Detecting Memory Exploits”, IEEE Transactions on Computers (TC), vol. 67, issue 8, 2018.
  • C. Nelson, K. Townsend, O. Attia, P. Jones and J. Zambreno. “RAMPS: A Reconfigurable Architecture for Minimal Perfect Sequencing”, IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 27, no. 10, 2016.
  • M. Awatramani, X. Zhu, J. Zambreno and D. Rover, “Phase Aware Warp Scheduling: Mitigating Effects of Phase Behavior in GPGPU Applications”, Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT), October, 2015.
  • O. Attia, K. Townsend, P. Jones and J. Zambreno, “A Reconfigurable Architecture for the Detection of Strongly Connected Components”, ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 9, no. 2, 2015.
  • A. Pande, S. Chen, P. Mohapatra and J. Zambreno. “Hardware Architecture for Video Authentication using Sensor Pattern Noise”, IEEE Transactions on Circuits and Systems for Video Technology (TCSVT), vol. 24, no. 1, pp. 157-167, 2014.

Primary Strategic Research Area

Secure Cyberspace & Autonomy