{"id":95,"date":"2016-01-12T16:10:27","date_gmt":"2016-01-12T22:10:27","guid":{"rendered":"http:\/\/www.engineering.iastate.edu\/people\/profile\/rlgeiger\/"},"modified":"2026-05-30T20:02:18","modified_gmt":"2026-05-31T01:02:18","slug":"rlgeiger","status":"publish","type":"profile","link":"https:\/\/www.engineering.iastate.edu\/people\/profile\/rlgeiger\/","title":{"rendered":"Geiger, Randall"},"author":308,"template":"","affiliation":[4],"department":[1121,7],"group":[1265,1254,1268],"interest":[58,56,57,59,60,61],"class_list":["post-95","profile","type-profile","status-publish","hentry","affiliation-faculty","department-ece-faculty","department-ecpe","group-cyber-infrastructure","group-ece-research-groups","group-materials-devices-circuits","interest-analog-and-mixed-signal-testing-and-bist","interest-analog-hardware-trojans","interest-cyber-security","interest-data-converter-design-and-testing","interest-reliability-and-yield-enhancement-of-semiconductor-devices","interest-temperature-sensors-and-voltage-references"],"firstname":"Randall","key_research_area":"","netid":"rlgeiger","isu_title":"Professor [E CPE]","email":"rlgeiger@iastate.edu","external_link":"","hide_isu_title":"1","nickname":"","info":"<h4 id=\"education-header\" class=\"dir-header\">Education:<\/h4>\r\n<div>\r\n<p style=\"padding-left: 30px;\">Ph.D., Electrical Engineering, Colorado State University (1977)<\/p>\r\n<p style=\"padding-left: 30px;\">M.S., Mathematics, University of Nebraska (1973)<\/p>\r\n<p style=\"padding-left: 30px;\">B.S., Electrical Engineering, University of Nebraska (1972)<\/p>\r\n\r\n<\/div>\r\n<h4 id=\"interest-header&quot;\" class=\"dir-header\">Research Areas:<\/h4>\r\n<div>\r\n<p style=\"padding-left: 30px;\"><em><strong>Core Area(s):<\/strong> <\/em>VLSI, secure and reliable computing, analog VLSI design, VLSI testing, high-speed data converters<\/p>\r\n<p style=\"padding-left: 30px;\"><em><strong>Department's Strategic Area(s):<\/strong><\/em> Materials, devices, &amp; circuits; cyber infrastructure<\/p>\r\n<strong><a href=\"http:\/\/class.ece.iastate.edu\/rlgeiger\/\">Additional Information<\/a><\/strong>\r\n\r\n&nbsp;\r\n\r\n<\/div>","middle_name":"","isu_office":"2133 Coover $ 2520 Osborn Dr. # Ames, IA 500111046","uid":[],"hide_isu_office":"0","lastname":"Geiger","publications":"<strong>Google Scholar Profile:\u00a0<\/strong><a href=\"https:\/\/scholar.google.com\/citations?user=f-GCFyQAAAAJ&amp;hl=en\">https:\/\/scholar.google.com\/citations?user=f-GCFyQAAAAJ&amp;hl=en<\/a>\r\n<ul>\r\n \t<li>Jin, L., D. Chen, and R. L. Geiger. SEIR Linearity Testing of Precision A\/D Converters in Non-stationary Environments with Center-Symmetric Interleaving. <em>IEEE Transactions on Instruction and Measurement,<\/em> October 2007, 1776-1785. Jiang, H., B. Olleta, D. J. Chen, and R. L. Geiger. Testing High- Resolution ADCs with Low-Resolution\/Accuracy Deterministic Dynamic Element Matched DACs. <em>IEEE Transactions on Circuits and Systems I,<\/em> May 2007, 964-973.<\/li>\r\n \t<li>Oletta, B., H. Jiang, D. J. Chen, and R. L. Geiger. A Deterministic Dyanmic Element Mating Approach for Testing High-Resolution ADCs with Low Accuracy Excitations. <em>IEEE Transactions on Instruction and Measurement <\/em>55, no. 3, (June 2006): 902-915.<\/li>\r\n \t<li>Lin, Y., D. Chen, and R. L. Geiger. Yield Enhancement with Optimal Area Allocation for Radio-Critical Analog Circuits. <em>IEEE Transactions on Circuits and Systems <\/em>53, (March 2006): 534-553.\r\nCong and R. L. Geiger. A 1.5v 14-bit 100-MS\/s Self-Calibrated DAC. <em>IEEE Journal of Solid State Circuits <\/em>38, no. 12, (December 2003): 2051-2060.<\/li>\r\n<\/ul>","user_image":{"ID":"852","post_author":"0","post_date":"2016-01-14 22:51:12","post_date_gmt":"2016-01-15 04:51:12","post_content":"","post_title":"GeigerRandall","post_excerpt":"","post_status":"inherit","comment_status":"closed","ping_status":"closed","post_password":"","post_name":"geigerrandall","to_ping":"","pinged":"","post_modified":"2019-03-04 08:52:19","post_modified_gmt":"2019-03-04 14:52:19","post_content_filtered":"","post_parent":"95","guid":"http:\/\/www.engineering.iastate.edu\/people\/files\/2016\/01\/GeigerRandall.jpg","menu_order":"0","post_type":"attachment","post_mime_type":"image\/jpeg","comment_count":"0","pod_item_id":"852"},"user_title":"Tunc and Lale Doluca Professor in Electrical and Computer Engineering","phone_number":"515-294-7745","fax":"","office":"","_links":{"self":[{"href":"https:\/\/www.engineering.iastate.edu\/people\/wp-json\/wp\/v2\/profile\/95","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.engineering.iastate.edu\/people\/wp-json\/wp\/v2\/profile"}],"about":[{"href":"https:\/\/www.engineering.iastate.edu\/people\/wp-json\/wp\/v2\/types\/profile"}],"author":[{"embeddable":true,"href":"https:\/\/www.engineering.iastate.edu\/people\/wp-json\/wp\/v2\/users\/308"}],"version-history":[{"count":4,"href":"https:\/\/www.engineering.iastate.edu\/people\/wp-json\/wp\/v2\/profile\/95\/revisions"}],"predecessor-version":[{"id":16921,"href":"https:\/\/www.engineering.iastate.edu\/people\/wp-json\/wp\/v2\/profile\/95\/revisions\/16921"}],"wp:attachment":[{"href":"https:\/\/www.engineering.iastate.edu\/people\/wp-json\/wp\/v2\/media?parent=95"}],"wp:term":[{"taxonomy":"affiliation","embeddable":true,"href":"https:\/\/www.engineering.iastate.edu\/people\/wp-json\/wp\/v2\/affiliation?post=95"},{"taxonomy":"department","embeddable":true,"href":"https:\/\/www.engineering.iastate.edu\/people\/wp-json\/wp\/v2\/department?post=95"},{"taxonomy":"group","embeddable":true,"href":"https:\/\/www.engineering.iastate.edu\/people\/wp-json\/wp\/v2\/group?post=95"},{"taxonomy":"interest","embeddable":true,"href":"https:\/\/www.engineering.iastate.edu\/people\/wp-json\/wp\/v2\/interest?post=95"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}